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We've found 6 jobs for you

LanceSoft, Inc.  •  2025-02-02
  Markham, Ontario, I3P, CA

ASIC/RTL Design Engineer

Pay rate range: $75/hr to $90/hr on T4. Job Description: Responsibilities will include: • Design/implement various state-of-the-art, DDR PHYs (DDR5) • Deliver detailed specifications & documentation • Develop RTL and work closely with multiple cross func…

NETINT Technologies Inc.  •  2025-02-01
  Markham, Ontario, I3P, CA

ASIC Video Design Engineer (Remote in Canada or US)

About NETINT Technologies Inc. NETINT Technologies is a pioneer of computational storage and video processing SoC solutions for cloud and edge computing. Its Codensity portfolio enables enterprise, cloud data centers, and content providers to deploy high-perfo…

Intellectt Inc  •  2025-02-02
  Markham, Ontario, I3P, CA

System-on-Chip Design Engineer

KEY RESPONSIBILITIES: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraint…

L&T Technology Services  •  2025-02-03
  Markham, Ontario, I3P, CA

SoC Design Engineer

KEY RESPONSIBILITIES: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage designs. Owning timing flow and execution to meet SoC timing requirements including timing budgeting, repeater planning, constraint…

Intelliswift - An LTTS Company  •  2025-02-03
  Markham, Ontario, I3P, CA

Application Specific Integrated Circuit Design Engineer

Must Have skills: ASIC Implementation CAD STA Timing Synopsys DC / Primetime Scripting language, such as, TCL, Perl and/or Python KEY RESPONSIBILITIES: Developing block and SoC timing constraints, full chip STA setup and signoff of multi-corner multi-voltage d…

LanceSoft, Inc.  •  2025-02-02
  Markham, Ontario, I3P, CA

Design Verification Engineer

Pay rate range:$75/hr to $100/hr on T4 Job description: KEY RESPONSIBILITIES: • Develop/Maintain tests for functional verification with UVM verification at the subsystem level • Build testbench components to support the next generation IP • Maintain or i…