Design Verification Engineer
Pay rate range:$75/hr to $100/hr on T4 Job description: KEY RESPONSIBILITIES: • Develop/Maintain tests for functional verification with UVM verification at the subsystem level • Build testbench components to support the next generation IP • Maintain or i…
ASIC/RTL Design Engineer
Pay rate range: $75/hr to $90/hr on T4. Job Description: Responsibilities will include: • Design/implement various state-of-the-art, DDR PHYs (DDR5) • Deliver detailed specifications & documentation • Develop RTL and work closely with multiple cross func…
Validation Engineer
Note:- This is hardware validation role not a QA Automation/validation THE ROLE: The Datacenter Team is looking for dynamic and energetic Silicon Validation Engineers. As a key contributor to the time-to-market success of Client’s GPU based accelerators, you…