Roles & ResponsibilitiesAs a member of our team, you will work with multi-functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression.You will work with 3rd party IP vendors to integrate Memory B…

Block level design from RTL-to-GDSII: synthesis, floor-planning, place & route, timing/EMIR/PV closure, and signoffProficient with Cadence Implementation tool suite (Genus, Innovus)Controllers for High Speed IO IPs Structural implementation: datapaths, bus pla…