Pay rate -$80/hr on W2 Location : San Jose, CA Top 3 skills: Good understanding of SystemVerilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have- 8+ yea…

> THE ROLE:>>>> The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interfa…