Physical Design Engineer
5+ years of previous experience with PD Tools, flow, and design methodology from RTL synthesis to GDSII sign-off Experience with back-end design and timing closure on advanced process nodes (5nm and below) Experience with Cadence (Innovus, Genus) or Synopsys (…
SOC Design Verification Engineer
Job Description : Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UV…
Senior Design Verification Engineer
Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA ○ Develop test plans and coverage metrics from specifications and …
SOC Design Verification Engineer
Job Description : Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UV…
Senior Design Verification Engineer
Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA ○ Develop test plans and coverage metrics from specifications and …